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cmos ic ver:1.06 m2003 may 20, 2003 system-biz div. s.kubota 1/26 8-bit single chip microcontrolle r LC876796B/80b/72b LC876796B 8 bit single chip microcontroller incorporating 96kb rom and 2048 byte ram on chip lc876780b 8 bit single chip microcontroller incorporating 80kb rom and 2048 byte ram on chip lc876772b 8 bit single chip microcontroller incorporating 72kb rom and 2048 byte ram on chip overview the LC876796B/ lc876780b/ lc876772b are 8 bit single chip microcomputers with the following on-chip functional blocks: - cpu: operable at a minimum bus cycle time of 100ns - on-chip rom maximum capacity : LC876796B 96k bytes lc876780b 80k bytes lc876772b 72k bytes - on-chip ram: 2048 bytes - vfd automatic display controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / counter (can be divided into two 8 bit timers / two 8 bit pwm) - four 8 bit timer with prescaler - timer for use as date / time clock - high speed clock counter - system clock divider function - synchronous serial i/o port (with automatic block transmit / receive function) - asynchronous / synchronous serial i/o port - 14-channel 8-bit ad converter - weak signal detector - 21-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. ( datasheet : )
LC876796B/80b/72b 2/26 features (1) read-only memory (rom): LC876796B 98304 8 bits : lc876780b 81920 8 bits : lc876772b 73728 8 bits (2) random access memory (ram): LC876796B/80b/72b 2048 9 bits (3) minimum bus cycle time: 100ns (10mhz) note: the bus cycle time indicates rom read time. (4) minimum instruction cycle time (tcyc) : 300ns (10mhz) (5) ports - input/output ports data direction programmable for each bit individually : 20 (p1n, p70 to p73, p8n) - 15v withstand input/output ports data direction programmable in nibble units : 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) data direction programmable for each bit individually : 8 (p3n) - input ports : 2 (xt1,xt2) - vfd output ports large current outputs for digits : 9 (s0 / t0 to s8 / t8) large current outputs for digits / segments : 7 (s9 / t9 to s15 / t15) digit / segment outputs : 8 (s16 to s23) segment outputs : 28 (s24 to s51) other functions input/output ports : 12 (pfn, pg0 to pg3) input ports : 24 (pcn, pdn, pen) - oscillator pins : 2 (cf1,cf2) - reset pin : 1 (res#) - power supply : 6 (vss1 to 2, vdd1 to 4) (6) vfd automatic display controller - programmable segment/digit output pattern output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit waveforms). parallel-drive available for large current vfd. - 16-step dimmer function available (7) weak signal detection (mic signals etc) - counts pulses with width greater than a preset value - 2 bit counter (8) timers - timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register
LC876796B/80b/72b 3/26 - timer 1: pwm / 16 bit timer / counter with toggle output mode 0: 8 bit timer (with toggle output) + 8 bit timer / counter (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer / counter (with toggle output) toggle output also possible using the lower order 8 bits. mode 3: 16 bit timer (with toggle output) the lower order 8 bits can be used as pwm output. - timer 4: 8 bit timer with 6 bit prescaler - timer 5: 8 bit timer with 6 bit prescaler - timer 6: 8 bit timer with 6 bit prescaler - timer 7: 8 bit timer with 6 bit prescaler - base timer 1) the clock signal can be selected from any of the following. sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts can be selected to occu r at one of five different times. (9) high speed clock counter 1) capable of counting maximum: 20mhz clock (using main clock 10mhz) 2) real time output (10) serial-interface - sio 0: 8 bit synchronous serial interface 1) lsb first / msb first function available 2) internal 8 bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3) consecutive automatic data communication (1-256 bits) - sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2?512 tcyc) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8?2048tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2?512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) (11) ad converter -8 bits 14 channels (12) remote control receiver circuit (connected to p73/int3/t0in terminal) -noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 tcyc) (13) watchdog timer - the watching timer period is set using an external rc. - watchdog timer can produce interrupt, system reset.
LC876796B/80b/72b 4/26 (14) interrupts: 21-source, 10-vectored interrupts 1) three priority (low, high and highest) multiple interrupts are supported. during interrupt handling, an equal or lower priority interrupt request is refused. 2) if interrupt requests to two or more vector addre sses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/base timer/int5 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/mic/t6/t7 10 0004bh h or l vfd automatic display controller/port0/t4/t5 priority level: x>h>l for equal priority levels, vector with lowest address takes precedence. (15) subroutine stack levels: 1024 levels max. stack is located in ram. (16) multiplication and division - 16 bit 8 bit (executed in 5 cycles) - 24 bit 16 bit (12 cycles) - 16 bit 8 bit (8 cycles) - 24 bit 16 bit (12 cycles) (17) oscillation circuits - on-chip rc oscillation circuit for system clock use. - on-chip cf oscillation circuit for system clock use. (r f built in) - on-chip crystal oscillation circuit low speed system clock use. (rd, r f external) - on-chip frequency -variable rc oscillation circuit for system clock use (18) system clock divider function - able to reduce current consumption available minimum instruction cycle time: 300ns, 600ns, 1.2s, 2.4 s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s. (using 10mhz main clock) (19) standby function - halt mode halt mode is used to reduce power consumption. program execution is stopped. peripheral circuits still operate but vfd display and some serial transfer operations stop. 1) oscillation circuits are not stopped automatically. 2) release occurs on system reset or by interrupt.
LC876796B/80b/72b 5/26 -hold mode hold mode is used to reduce power consumption. both program execution and peripheral circuits are stopped. 1) cf, rc and crystal oscillation circuits stop automatically. 2) release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of int0, int1, int2, int4, int5 (3) an interrupt condition arises at port 0 -x?tal hold made x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits except the base timer are stopped. 1) cf and rc oscillation circuits stop automatically. 2) crystal oscillator is maintained in its state at hold mode inception. 3) release occurs on any an any of the following conditions (1) input to the reset pin goes low (2) a specified level is input to at least one of int0, int1, int2, int4, int5 (3) an interrupt condition arises at port 0 (4) an interrupt condition arises at the base-timer (20) factory shipment -delivery form qip100e (lead free product) (21) development tools - evaluation chip : lc876093 - emulator : eva62s + ecb876600 (evaluation chip board) + sub876700 + pod100qfp : ice-b877300 + sub876700 + pod100qfp - flash rom version: lc87f67c8a
LC876796B/80b/72b 6/26 pin assignment sanyo: qip100e (lead free product) s19/pc3 s18/pc2 s17/pc1 s16/pc0 vdd3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s48/pg0 s49/pg1 s50/pg2 s51/pg3 p00 p01 p02 p03 vss2 vdd2 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 vdd4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 fix0 p16/t1pwml p17/t1pwmh/buz p30/int4/t1in p31/int4/t1in p32/int4/t1in p33/int4/t1in p34/int5/t1in p35/int5/t1in p36/int5/t1in p37/int5/t1in res xt1/an10 xt2/an11 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin/an12 p73/int3/t0in/an13 s0/t0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LC876796B/80b/72b 7/26 system block diagram interrupt control stand-by control ir pla rom pc bus interface port 0 port 1 sio0 sio1 timer 0 (high speed clock counter) timer 1 base timer vfd controller int 0 - 5 noise rejection port 3 port 7 port 8 adc weak signal detector acc b register c register psw rar ram stack pointer watch dog timer alu timer 6 timer 7 timer 4 timer 5 clock generator cf rc x?tal mrc
LC876796B/80b/72b 8/26 pin assignment pin name i/o function option vss1 vss2 - ? power supply (-) no vdd1 vdd2 vdd3 vdd4 - ? power supply (+) no fix0 - ? test pin set as vss with the user?s option. (see note 1) no port0 p00 to p07 i/o ? 8bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ? 15v withstand at n-channel open drain output ye s port1 p10 to p17 i/o ? 8bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit ? other pin functions p10: sio0 data output p11: sio0 data input / bus input / output p12: sio0 clock input / output p13: sio1 data output p14: sio1 data input / bus input / output p15: sio1 clock input / output p16: timer 1 pwml output p17: timer 1 pwmh output / buzzer output ye s ? 8bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit ? 15v withstand at n-channel open drain output ? other functions: p30 to p33: int4 input / hold release input / timer 1 event input / timer 0l capture input / timer 0h capture input p34 to p37: int5 input / hold release input / timer 1 event input / timer 0l capture input / timer 0h capture input the following types of interrupt detection are possible: rising falling rising/ falling h level l level i n t4 ye s ye s ye s n o n o i n t5 ye s ye s ye s n o n o port3 p30 to p37 i/o ye s
LC876796B/80b/72b 9/26 pin name i/o function option ? 4bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit ? other functions p70: int0 input / hold release input / timer0l capture input / output for watchdog timer p71: int1 input / hold release input / timer0h capture input p72: int2 input / hold release input / timer 0 event input / timer0l capture input / high speed clock counter input p73: int3 input(noise rejection filter attached input) / timer 0 event input / timer 0h capture input ad input port: an8(p70), an9(p71), an12(p72), an13(p73) the following types of interrupt detection are possible: rising falling rising/ falling h level l level i n t0 ye s ye s n o ye s ye s i n t1 ye s ye s n o ye s ye s i n t2 ye s ye s ye s n o n o i n t3 ye s ye s ye s n o n o port7 p70 to p73 i/o no port8 p80 to p87 i/o ? 8bit input/output port ? input/output can be specified in a bit unit ? other functions: ad input port: an0 to an7 weak signal detector input port: micin(p87) no s0/t0 to s8/t8 o ? large current output for vfd display controller digit (can be used for segment) no s9/t9 to s15/t15 o ? large current output for vfd display controller segment/digit no s16 to s23 i/o ? output for vfd display controller segment/digit ? other functions: high voltage input port: pc0 to pc7 no s24 to s31 i/o ? output for vfd display controller segment ? other functions: high voltage input port: pd0 to pd7 no s32 to s39 i/o ? output for vfd display controller segment ? other functions high voltage input port: pe0 to pe7 no s40 to s47 i/o ? output for vfd display controller segment ? other functions: high voltage input/output port: pf0 to pf7 no s48 to s51 i/o ? output for vfd display controller segment ? other functions: high voltage input/output port: pg0 to pg3 no res i reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? other functions: general purpose input port when not in use, connect to vdd1. ad input port: an10 no
LC876796B/80b/72b 10/26 pin name i/o function option xt2 i/o ? output for 32.768khz crystal oscillation ? other functions: general purpose input port when not in use, set to oscillation mode and leave open circuit. ad input port: an11 no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no note 1: the lc876700 series can be mounted onto the circuit board intended for the lc876500 and lc876600 series. in this case, the minus voltage of the vfd power supply is supplied to the fix0 pin. using a negative voltage does not alter the fix0 pin?s operation.
LC876796B/80b/72b 11/26 port output configuration output configuration and pull-up/pull-down resistor options are shown in the following table. input/output is possible even when port is set to output mode. terminal option applies to: options output format pull-up resistor pull-down resistor 1 cmos programmable (note 1) - p00 to p07 1 bit units 2 15v nch-open drain none - 1 cmos programmable - p10 to p17 each bit 2 nch-open drain programmable - 1 cmos programmable - p30 to p37 each bit 2 15v nch-open drain none - p70 - none nch-open drain programmable - p71 to p73 - none cmos programmable - p80 to p87 - none nch-open drain none - s0/t0 to s15/t15 s16 to s51 - none high voltage pch-open drain - none xt1 - none input only none - xt2 - none output for 32.768khz crystal oscillation none - note 1: programmable pull-up resisters of port 0 can be attached in nibble units (p00-03, p04-07). * note 1: connect as follows to reduce noise on vdd and increase the back-up time. vss1, and vss2 must be conn ected together and grounded. * note 2: the power supply for the internal memory is vdd1 but it uses the vdd2 as the power supply for ports. when the vdd2 is not backed up, the port level does not become ?h? even if the port latch is in the ?h? level. therefore, when the vdd2 is not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shorter because the through current runs from vdd to gnd in the input buffer. if vdd2 is not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. back-up capacitors power supply lsi vdd1 vdd2 vdd3 vss2 vss1 vdd4 vfd powers
LC876796B/80b/72b 12/26 1. absolute maximum ratings / ta=25c and vss1=vss2=0v limits parameter symbol pins conditions vdd [v] min. typ. max. unit supply voltage vddmax vdd1,vdd2, vdd3,vdd4 vdd1=vdd2= vdd3=vdd4 -0.3 +7.0 vi(1) xt1,xt2,cf1, res -0.3 vdd+0.3 input voltage vi(2) fix0 vdd-45 vdd+0.3 output voltage vo(1) s0/t0 to s15/t15 vdd-45 vdd+0.3 vio(1) ?port 0: cmos output option ?port 1 ?port 3: cmos output option ?port 7 ?port 8 -0.3 vdd+0.3 vio(2) ?port 0 open drain ?port 3 open drain -0.3 15 input/output voltage vio(3) s16 to s51 vdd-45 vdd+0.3 v ioph(1) port 0, 1, 3 ?cmos output selected ?current at each pin -10 ioph(2) port 71,72,73 current at each pin -3 ioph(3) s0/t0 to s15/t15 current at each pin -30 peak output current ioph(4) s16 to s51 current at each pin -15 ioah(1) port 0 total of all pins -30 ioah(2) port 1,3 total of all pins -30 ioah(3) port 7 total of all pins -5 ioah(4) s0/t0 to s15/t15 total of all pins -65 ioah(5) s16 to s27 total of all pins -60 ioah(6) s28 to s39 total of all pins -60 high level output current total output current ioah(7) s40 to s51 total of all pins -60 iopl(1) port 0,1,3 for each pin 20 peak output current iopl(2) port 7,8 for each pin 5 ioal(1) port 00,01,02,03 total of all pins 50 ioal(2) ?port 04,05,06,07 ?port 1,3 total of all pins 50 low level output current total output current ioal(3) ports 7,8 total of all pins 20 ma maximum power dissipation pdmax qip100e ta = -30 to+70c 502 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
LC876796B/80b/72b 13/26 2. recommended operating range / ta=-30c to +70c, vss1=vss2=0v limits parameter symbol pins conditions vdd [v] min. typ. max. unit operating supply voltage range vdd(1) vdd1=vdd2=vdd3 =vdd4 0.294s ?? tcyc ?? 200s 4.5 6.0 hold voltage vhd vdd1 ram and the register data are kept in hold mode. 2.0 6.0 vih(1) ?port 0,3: cmos output option ?port 8 output disable 4.5?6.0 0.3vdd +0.7 vdd vih(2) port 0,3: n-ch open drain output output disable 4.5?6.0 0.3vdd +0.7 13.5 vih(3) ?port 1 ?port 71,72,73 ?p70 port input/ interrupt output disable 4.5?6.0 0.3vdd +0.7 vdd vih(4) s16 to s51 output p-channel tr. off 4.5?6.0 0 .33vdd +1.0 vdd vih(5) port 87 weak signal input output disable 4.5?6.0 0 .75vdd vdd vih(6) port 70 watchdog timer output disable 4.5?6.0 0.9vdd vdd input high voltage vih(7) xt1, xt2, cf1, res 4.5?6.0 0 .75vdd vdd vil(1) ?port 0,3: cmos output option ?port 8 output disable 4.5?6.0 vss 0.15vdd +0.4 vil(2) port 0,3: n-ch open drain output output disable 4.5?6.0 vss 0.15vdd +0.4 vil(3) ?port 1 ?port 71,72,73 ?p70 port input / interrupt output disable 4.5?6.0 vss 0.1vdd +0.4 vil(4) s16 to s51 output p-channel tr. off 4.5?6.0 -35 0.2vdd vil(5) port 87 weak signal input output disable 4.5?6.0 vss 0.25vdd vil(6) port 70 watchdog timer output disable 4.5?6.0 vss 0.8vdd -1.0 input low voltage vil(7) xt1,xt2,cf1, res 4.5?6.0 vss 0.25vdd v operation cycle time t cyc 4.5?6.0 0.294 200 s ?cf2 open circuit ?system clock divider set to 1/1 ?external clock duty = 505% 4.5?6.0 0.1 10 external system clock frequency fexcf(1) cf1 ?cf2 open circuit ?system clock divider set to 1/2 4.5?6.0 0.2 20 mhz continued
LC876796B/80b/72b 14/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5?6.0 10 fmcf(2) cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 4.5?6.0 4 fmrc rc oscillation 4.5?6.0 0.3 1.0 2.0 fmmrc frequency variable rc oscillation 4.5-6.0 50 mhz oscillation stabilizing time period (note 1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 4.5?6.0 32.768 khz (note 1) the oscillation constant is shown in table 1 and table 2.
LC876796B/80b/72b 15/26 3. electrical characteristics / ta=-30c to +70c, vss1=vss2=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0,3: n-ch open drain output ?output disable ?vin=13.5v (including off state leak current of the output tr.) 4.5?6.0 5 iih(2) port 0,1,3,7,8 ?output disable ?pull-up resister off. ?vin=vdd (including off state leak current of the output tr.) 4.5?6.0 1 iih(3) s16 to s51 (port c,d,e,f,g) when configured as an input port vin=vdd 4.5?6.0 60 iih(4) res vin=vdd 4.5?6.0 1 iih(5) xt1,xt2 when configured as an input port vin=vdd 4.5?6.0 1 iih(6) cf1 vin=vdd 4.5?6.0 15 input high current iih(7) p87/an7/micin weak signal input vin=vbis+0.5v (vbis : bias voltage) 4.5?6.0 4.2 8.5 15 iil(1) port 0,1,3,7,8 ?output disable ?pull-up resister off. ?vin=vss (including off state leak current of the output tr.) 4.5?6.0 -1 iil(2) res vin=vss 4.5?6.0 -1 iil(3) xt1,xt2 when configured as an input port vin=vss 4.5?6.0 -1 iil(4) cf1 vin=vss 4.5?6.0 -15 input low current iil(5) p87/an7/micin weak signal input vin=vbis-0.5v (vbis : bias voltage) 4.5?6.0 -15 -8.5 -4.2 a voh(1) ioh=-1.0ma 4.5?6.0 vdd-1 voh(2) port 0,1,3: cmos output option ioh=-0.1ma 4.5?6.0 vdd-0.5 voh(3) port 7 ioh=-0.4ma 4.5?6.0 vdd-1 voh(4) ioh=-20.0ma 4.5?6.0 vdd-1.8 voh(5) s0/t0 to s15/t15 ioh=-1.0ma ioh at any single pin is not over 1ma. 4.5?6.0 vdd-1 voh(6) ioh=-5.0ma 4.5?6.0 vdd-1.8 output high voltage voh(7) s16 to s51 ioh=-1.0ma ioh at any single pin is not over 1ma. 4.5?6.0 vdd-1 vol(1) iol=10ma 4.5?6.0 1.5 vol(2) port 0,1,3 iol=1.6ma 4.5?6.0 0.4 output low voltage vol(3) port 7,8 iol=1ma 4.5?6.0 0.4 v pull-up resistor rpu port 0,1,3,7 voh=0.9vdd 4.5?6.0 15 40 70 k ? continued
LC876796B/80b/72b 16/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit ioff(1) ?output p-ch tr. off ?vout=vss 4.5?6.0 -1 output off- leak current ioff(2) s0/t0 to s15/t15, s16 to s51 ?output p-ch tr. off ?vout=vdd-40v 4.5?6.0 -30 a resistance of the low level hold tr. rinpd s16 to s51 ?output p-ch tr. off 4.5?6.0 200 k ? vhis(1) ?port 1,7 ? res 4.5?6.0 0.1vdd hysteresis voltage vhis(2) port 87 weak signal input 4.5?6.0 0.1vdd v pin capacitance cp all pins ?all other terminals connected to vss. ?f=1mhz ?t a =25c 4.5?6.0 10 pf input sensitivity vsen port 87 weak signal input 4.5?6.0 0.12vdd vpp
LC876796B/80b/72b 17/26 4. serial input/output characteristics / ta=-30c to +70c, vss1=vss2=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit cycle time tsck(1) 4/3 tsckl(1) 2/3 low level pulse width tsckla(1) 2/3 tsckh(1) 2/3 high level pulse width tsckha(1) sck0(p12) refer to figure 6 4.5?6.0 5 cycle time tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1(p15) refer to figure 6 4.5?6.0 1 cycle time tsck(3) 4/3 t cyc tsckl(3) 1/2 low level pulse width tsckla(2) 3/4 tsckh(3) 1/2 high level pulse width tsckha(2) sck0(p12) ?cmos output option ?refer to figure 6 4.5?6.0 2 tsck cycle time tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ?cmos output option ?refer to figure 6 4.5?6.0 1/2 tsck data set-up time t sdi 0.03 serial input data hold time t hdi si0(p11), si1(p14), sb0(p11), sb1(p14) ?measured with respect to si0clk leading edge. ?refer to figure 6 4.5?6.0 0.03 serial output output delay time tddo so0(p10), so1(p13), sb0(011), sb1(p14) ?measured with respect to si0clk trailing edge. ?when port is open drain: time delay from si0clk trailing edge to the so data change. ?refer to figure 6 4.5?6.0 1/3 tcyc +0.05 s
LC876796B/80b/72b 18/26 5. pulse input conditions / ta=-30c to +70c, vss1=vss2=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p30 to p33) int5(p34 to p37) ?interrupt acceptable ?events to timer 0,1 can be input. 4.5?6.0 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio set to 1/1.) ?interrupt acceptable ?events to timer 0 can be input. 4.5?6.0 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio set to 1/32.) ?interrupt acceptable ?events to timer 0 can be input. 4.5?6.0 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio set to 1/128.) ?interrupt acceptable ?events to timer 0 can be input. 4.5?6.0 256 tpih(5) tpil(5) micin(p87) ?weak signal detection counter enabled 4.5?6.0 1 tpih(6) tpil(6) nkin(p72) ?high speed clock counter countable 4.5?6.0 1/12 t cyc high/low level pulse width tpil(7) res ?reset possible 4.5?6.0 200 s 6. ad converter characteristics / ta=-30c to + 70c, vss1=vss2=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5?6.0 8 bit absolute precision et (note2) 4.5?6.0 1.5 lsb ad conversion time = 32 tcyc (adcr2=0) (note 3) 15.62 (tcyc= 0.488s) 97.92 (tcyc= 3.06s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 4.5?6.0 18.82 (tcyc= 0.294s) 97.92 (tcyc= 1.53s) s analog input voltage range vain 4.5?6.0 vss vdd v iainh vain=vdd 4.5?6.0 1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2), an12(p72), an13(p73) vain=vss 4.5?6.0 -1 a (note 2) absolute precision not including quantizing error (1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register.
LC876796B/80b/72b 19/26 7. current dissipation characteristics / ta=-30c to +70c, vss1=vss2=0v limits parameter symbol pins conditions vdd[v] min. typ. max unit iddop(1) ?fmcf=10mhz for ceramic resonator oscillation ?fsx?tal=32.768khz for crystal oscillation ?system clock: cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider set to 1/1 4.5?6.0 9.5 30 iddop(2) ?cf1=20mhz for external clock ?fsx?tal=32.768khz for crystal oscillation ?system clock: cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider set to 1/2 4.5?6.0 10.5 31 iddop(3) ?fmcf=4mhz ceramic resonator oscillation ?fsx?tal=32.768khz for crystal oscillation ?system clock: cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider set to 1/1 4.5?6.0 4.2 17 iddop(4) ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz for crystal oscillation ?frequency variable rc oscillation stopped. ?system clock: rc oscillation ?divider set to 1/2 4.5?6.0 1 10 iddop(5) ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz for crystal oscillation ?internal rc oscillation stopped. ?system clock: 1mhz with frequency variable rc oscillation ?divider set to 1/2 4.5?6.0 2 12 ma current dissipation during basic operation (note 4) iddop(6) vdd1 = vdd2 = vdd3 = vdd4 ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz for crystal oscillation ?system clock: 32.768khz ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider set to 1/2 4.5?6.0 40 140 a continued
LC876796B/80b/72b 20/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode ?fmcf=10mhz for ceramic resonator oscillation ?fsx?tal=32.768khz for crystal oscillation ?system clock : cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider: 1/1 4.5?6.0 4 12 iddhalt(2) halt mode ?cf1=20mhz for external clock ?fsx?tal=32.768khz for crystal oscillation ?system clock : cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider 1/2 4.5?6.0 4.8 13 iddhalt(3) halt mode ?fmcf=4mhz for ceramic resonator oscillation ?fsx?tal=32.768khz for crystal oscillation ?system clock : cf oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider: 1/1 4.5?6.0 1.8 6 ma iddhalt(4) halt mode ?fmcf=0hz (when oscillation stops.) ?fsx?tal=32.768khz for crystal oscillation ?frequency variable rc oscillation stopped. ?system clock : rc oscillation ?divider: 1/2 4.5?6.0 500 1600 current dissipation halt mode (note 4) iddhalt(5) vdd1= vdd2= vdd3= vdd4 halt mode ?fmcf=0hz (when oscillation stops.) ?fsx?tal=32.768khz for crystal oscillation ?internal rc oscillation stopped. ?system clock: 1mhz with frequency variable rc oscillation ?divider: 1/2 4.5?6.0 1500 3600 a continued
LC876796B/80b/72b 21/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit current dissipation halt mode (note 4) iddhalt(6) vdd1= vdd2= vdd3= vdd4 halt mode ?fmcf=0hz (when oscillation stops.) ?fsx?tal=32.768khz for crystal oscillation ?system clock : 32.768khz ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped. ?divider: 1/2 4.5?6.0 25 100 current dissipation hold mode iddhold(1) vdd1 hold mode ?cf1=vdd or open circuit (when using external clock) 4.5?6.0 0.05 25 current dissipation date/time clock hold mode iddhold(2) vdd1 date/time clock hold mode ?cf1=vdd or open circuit (when using external clock) ?fsx?tal=32.768khz for crystal oscillation 4.5?6.0 20 90 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
LC876796B/80b/72b 22/26 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 ?m pf ?n c2 ?m pf ?n rd1 ?m???n operating supply voltage range ?m v ?n typ ?m?? s ?n max ?m?? s ?n notes cstls10m0g53-b0 (15) (15) 150 4.5~6.0 0.04 0.25 built in c1,c2 10mhz murata cstce10m0g52-r0 (10) (10) 150 4.5~6.0 0.04 0.25 built in c1,c2 cstls4m00g56-b0 (47) (47) 220 4.5~6.0 0.15 0.5 built in c1,c2 4mhz murata cstcr4m00g55-r0 (39) (39) 0 4.5~6.0 0.05 0.3 built in c1,c2 the oscillation stabilizing time is a period until the oscillation becomes stable after vdd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 2. subsystem clock oscillation circuit characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 ?m pf ?n c4 ?m pf ?n rf ?m???n rd2 ?m???n operating supply voltage range ?m v ?n typ ?m s ?n max ?m s ?n notes 32.768khz seiko epson the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (refer to figure4) (notes) ? since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1
LC876796B/80b/72b 23/26 figure 3 ac timing measurement point reset time and oscillation stable time hold release signal and oscillation stable time figure 4 oscillation stablization time 0.5vdd power supply res internal rc oscillation cf1 , cf2 xt1 , xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution vdd vdd limit 0v internal rc oscillation cf1,cf2 xt1,xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsxtal hold halt
LC876796B/80b/72b 24/26 figure 5 reset circuit figure 6 serial input / output test condition (note) set c res , r res values such that reset time exceeds 200s. c res vdd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
LC876796B/80b/72b 25/26 figure 7 pulse input timing condition tpil tpih
LC876796B/80b/72b ps 26 / 26 this catalog provies information as of november 2001. specifications and information herein are subject to change without notice

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